Integrated circuits (ICs) can include millions of semiconductor devices, such as non-volatile memory devices. Though existing fabrication systems have the capability of fabricating millions of semiconductor devices in an integrated circuit, there is still a need to decrease the size of IC device features so that the number of devices on an IC may be increased.
Conventional photolithographic techniques represent one limitation to the size of critical dimensions associated with devices in an IC. Conventional photolithographic techniques are used to transfer patterns onto semiconductor devices so that desired structures can be fabricated. Typically, a device layer, in which structures are to be formed, is coated with a layer of photo-resist material and a radiation source is used to expose selected areas of the surface of the photo-resist. Exposure of the photo-resist layer causes an image area, corresponding to the desired pattern, to be more soluble in a particular developer. The more soluble areas may be removed in a conventional developing process to leave the patterned image in the photo-resist layer. An etching process may then be applied to the patterned photo-resist layer to remove selected portions of the underlying device layer to form the desired structures in the device layer.
One problem with conventional photolithographic techniques is that reflectively of the layers being patterned can cause large variations in critical dimensions (CDs) of the devices being fabricated. Conventionally, a layer of anti-reflective coating (ARC) has been used to attempt to minimize the variations in critical dimensions that occur due to the reflectivity of the layers being patterned. A substantial swing in device critical dimensions, however, may still occur using the ARC layer in existing photolithographic techniques.